Ever since the introduction of the microprocessor, computer systems have been getting faster and faster. In approximate accordance with Moore's law (based on Intel® Corporation co-founder Gordon Moore's 1965 publication predicting the number of transistors on integrated circuits to double every two years), the speed increase has shot upward at a fairly even rate for nearly three decades. At the same time, the size of both memory and non-volatile storage has also steadily increased, such that many of today's personal computers are more powerful than supercomputers from just 10-15 years ago.
Historically, computer architectures employed discrete components, such as Central Processing Units (CPU, aka processors), memory controllers or hubs, IO (Input-Output) controllers or hubs, etc., that were interconnects via bus and/or interconnect wiring embedded on a board one which the discrete components were installed. In recent years, these conventional architectures have been superseded by System on a Chip (SoC) architectures, where various Intellectual Property (IP) blocks are interconnected via one or interconnect fabrics. As used herein, an IP block is representative of a block or logical group of circuitry that typically serves one or more targeted functions and may comprise logic that is either developed in-house or licensed from a third-party. IP blocks are also commonly referred to as functional blocks or “IP.” The interconnect fabrics may typically comprise multiple point-to-point interconnects between various IP block endpoints, a cross-bar type interconnect (both commonly referred to as mesh-based fabrics), or a ring-type interconnect that includes multiple interconnect segments coupled between nodes on the ring that are coupled to the various IP blocks.
On one level, fabric interconnects operate similar to a computer network, wherein a multiple layer protocol is employed to transfer data between end points. For example, multiple IP blocks may be connected to a fabric, either directly or indirectly (e.g., via a bridge or other intermediary component) in a manner roughly analogous with multiple computers connected to a Local Area Network (LAN). To transfer data between a pair of IP blocks, a multilayer protocol is employed including address information such as source and destination addresses in a manner analogous to an IP network (noting the address format is different, among other differences). Like a LAN, the fabric includes interface (i.e., fabric ports) to which the IP blocks are connected, and facilitates switching/routing/forwarding of data between sending and receiving IP blocks, which may also be referred to as (network) nodes. In view of these similarities, integrated circuits employing these architectures are sometimes referred to as Network on a Chip (NoC) architectures, and the fabric interconnects may be referred to as fabric switches that facilitate data transfers between IP blocks comprising nodes coupled to the fabric.
Under a standard implementation of an on-chip fabric, the fabric routing tables or routing logic is configured in a static manner, where based on a certain field or fields of the packet entering the fabric (e.g., destination address) the packet destination will be a certain node or nodes. In cases where the destination node is powered down, should not receive the data due to security considerations or does not support the type of traffic forwarded to it the packet is either discarded or a notification is sent to the originator that the transaction failed, requiring software intervention. Such occurrences frequently lead to system crashes and/or “Blue Screen of Death” (BSoD) events.